In general, when a field effect transistor is designed to operate at a high frequency, the gate electrode of the field effect transistor tends to be shrunk in length. This results in that a signal on the gate electrode is subjected to a large resistance during propagation. One well known solution is the use of a overlay type gate electrode which has a T-shaped configuration. A typical example of a MES type field effect transistor with the overlay type gate electrode is illustrated in FIG. 1 of the drawings. In FIG. 1, reference numeral 1 designates a gallium-arsenide semi-insulating substrate and a gate electrode 2 of a tungsten silicide (WSi) is formed on the upper surface of the semi-insulating substrate 1. The upper surface of the semi-insulating substrate has an exposed area on the both sides of the gate electrode 2, and the exposed area is covered with an oxide layer 3. On the gate electrode 2 is formed a multiple metal layer 4 which is longer in length than the gate electrode 2, so that the multiple metal layer 4 has an outer peripheral portion 5 projecting from the outer peripheral of the gate electrode 2. In this prior-art example, the multiple metal layer 4 has a titanium film, a platinum film and an aurum film.
The process of fabricating the MES type field effect transistor illustrated in FIG. 1 starts with preparation of the gallium-arsenide semi-insulating substrate 1, and the gate electrode 2 is formed by a deposition of tungsten silicide followed by a lithography techniques. After formation of the gate electrode 2, the oxide layer 3 is formed on the exposed area of the semi-insulating substrate 1 so as to create a smooth topography and, thereafter, the multiple metal layer 4 is deposited and etched to form the overlay gate structure.
The MES type field effect transistor illustrated in FIG. 1 has the gate structure with a low resistance by virtue of the multiple metal layer 4, however a problem is encountered in a large parasitic capacitance due to direct contact with the oxide layer 3.
In order to reduce the parasitic capacitance encountered in the MES type field effect transistor illustrated in FIG. 1 of the drawings, another MES type field effect transistor is proposed, and the structure thereof is illustrated in FIG. 2 of the drawings. Referring now to FIG. 2 of the drawings, the MES type field effect transistor illustrated in FIG. 2 comprises a semi-insulating substrate 11, a gate electrode 12 formed on the upper surface of the semi-insulating substrate 11, a conductive metal layer 13 provided on the gate electrode 12, and a thin insulating film 14. The metal layer 13 is longer in length than the gate electrode 12 so that the metal layer 13 has an outer peripheral portion 15 projecting from the outer peripheral of the gate electrode 12. Most of the upper surface of the semi-insulating substrate 11 is covered with the thin insulating layer 14, however the semi-insulating substrate 11 has an exposed portion under the metal layer 15 because of the outer peripheral portion 15 of the metal layer 15. This is because of the fact that the thin insulating layer 14 is deposited on the upper surface of the semi-insulating substrate 11 after formation of the conductive metal layer 13. Namely, the process of fabrication starts with preparation of the semi-insulating substrate 11, and the gate electrode 12 is formed on the semi-insulating substrate 11. After the gate electrode 12 is formed on the upper surface of the semi-insulating substrate 11, an oxide film ( not shown ) is deposited to create a smooth topography. The formation of the conductive metal layer 13 follows, and, thereafter, the oxide film is etched away to expose the upper surface of the semi-insulating substrate 11. When the upper surface of the semi-insulating substrate 11 is exposed, the thin insulating film 14 is deposited on the exposed upper surface of the semi-insulating substrate 11 for protection. However, the metal layer with the outer peripheral portion 15 has been already formed on the gate electrode 12, so that the thin insulating film 14 hardly covers the entire exposed upper surface under the outer peripheral portion 15. This results in that the MES type field effect transistor illustrated in FIG. 2 has an exposed area under the outer peripheral portion 15 of the metal layer 13 even if the thin insulating film 14 is applied to the upper surface of the semi-insulating substrate 11. For this reason, the MES structure illustrated in FIG. 2 is free from the large parasitic capacitance, however another problem is encountered in the MES structure illustrated in FIG. 2 in incomplete protection film of the upper surface of the semi-insulating substrate 11.